1. Technical Field
This art is related to a power compensation for a circuit.
2. Background
Recent integrated circuits tend to lower an operating voltage in order to meet needs for high speed operation, whereas the current consumptions in the integrated circuits tend to increase with an increase in scale.
To keep the power consumption of a large scale integrated circuit low, a power-gating technique, a clock-gating technique, and a dynamic potential control technique are available. Those technique cause an increase in power supply noise generated when a circuit switches from a sleep mode to an active mode.
To cope with the increase in power supply noise, a high voltage power supply, a switch, and a level shifter are mounted on a power supply circuit. Accordingly, when a logic circuit wakes up, the level shifter allows the switch to be turned on to connect the logic circuit to the high voltage power supply, thus charging a decoupling capacitor connected in parallel to the logic circuit. Consequently, power supply voltage variation in the logic circuit can be suppressed upon waking up. Such a method of suppressing power supply voltage variation is disclosed in, for example, Y. Nakamura et al. “An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise”, Symposium on VLSI Circuits, pp. 124-125, FIG. 1, 2007.
In addition, an auxiliary decoupling capacitor, a power supply having a potential higher than that of a power supply driving a microprocessor, and a switch are mounted on the power supply circuit. The auxiliary decoupling capacitor is charged by the power supply. When the microprocessor enters a transient state, the switch is turned on, so that current is supplied from the auxiliary decoupling capacitor to the microprocessor. Consequently, the current supplied from the decoupling capacitor to the microprocessor can be suppressed, thus preventing a voltage spike from occurring when the microprocessor enters the transient state. Such a method of suppressing a voltage spike is disclosed in, for example, L. Amoroso et al. “Single Shot Transient Suppressor (SSTS) for High Current High Slew Rate Microprocessor”, Applied Power Electronics Conf. and Exposition, vol. 1, pp. 284-288, FIG. 3.1, March 1999.
In the above-described method of suppressing power supply voltage variation, however, the high voltage power supply supplies current to the decoupling capacitor in a chip through an inductor arranged outside the chip. Accordingly, the charging time of the decoupling capacitor through the high voltage power supply depends on the resonant frequency of the inductor and the decoupling capacitor. Since the inductance of the inductor outside the chip is very high, it is difficult for the logic circuit operating at high speed to ensure an adequate charging rate. Unfortunately, the power supply voltage varies.
In the above-described method of suppressing a voltage spike, the current is supplied from the auxiliary decoupling capacitor, having a capacitance Ce, to the microprocessor through a resistor whose resistance R1 is parasitic on a transistor switch. Therefore, the charging time of the decoupling capacitor, having a capacitance Cd, of the microprocessor is determined by the time constant of the capacitance Ce of the auxiliary decoupling capacitor and the resistance R1. The capacitance Ce needs to be very high. The time constant is obtained as the product of the capacitance Ce and the resistance R1. Therefore, it is difficult to quickly suppress a voltage spike.